Ground sensing or VDD sensing schemes of DRAM circuits provide many advantages in improving memory performance. However, such sensing schemes require a unique reference cell for providing a reference voltage for sensing. A conventional reference cell in a DRAM circuit generally comprises two access transistors and a single capacitor. In order to differentiate reference cell data from the memory cell data and provide a reference voltage, the reference cell requires a particular power supply voltage. It is difficult to obtain a stable, high current power supply voltage for the reference cell capacitor. Consequently, using such a power supply voltage as a sensing reference creates a lot of noise and degrades the sensing operation and memory performance. In the following, a memory circuit according to the art will be described.
FIG. 1 shows a memory device as disclosed in U.S. Pat. No. 6,914,840. The DRAM circuit comprises a memory cell having a memory cell capacitor and a reference cell having a reference cell capacitor. Referring to FIG. 1, the NMOS-type DRAM circuit 10 includes a memory cell 11, a CMOS sense amplifier 12, a precharge circuit 13, and a dummy cell 14. The memory cell 11 is at the intersection of a word line WL and a bit line BL. The CMOS sense amplifier 12 serves to sense and amplify a potential difference between the pair of bit lines BL and BLX. The precharge circuit 13 precharges the bit line pair BL and BLX. The dummy cell 14 is provided at the intersection of a dummy word line DWL and the bit line BLX. The memory cell 11 is a 1-transistor cell composed of an NMOS transistor 111 and a main capacitor 112. The NMOS transistor 111 is turned on by activating the word line WL while the bit line BL is inactive, thereby electrically coupling the main capacitor 112 to the bit line BL.
The sense amplifier 12, which is activated by activation of a signal line SAP, detects a potential difference caused between the bit line pair BL and BLX, and puts one of the bit line pair BL and BLX to a power supply voltage VDD (the activation voltage of the signal line SAP), while putting the other to a GND level. The precharge circuit 13, which is activated by activating a signal line PRE when the word line WL and the dummy word line DWL are inactive, precharges the bit line pair BL and BLX to the GND level. The dummy cell 14 is composed of NMOS transistors 141 and 142 and a dummy capacitor 143. The NMOS transistor 141 is turned on by activation of the dummy word line DWL, whereby the dummy capacitor 143 is electrically coupled with the bit line BLX. The NMOS transistor 142 is turned on by activating the precharge-signal-supplying signal line PRE when the dummy word line DWL is inactive, thereby electrically coupling the dummy capacitor 143 and a voltage line VPRE with each other. The voltage line VPRE supplies the power supply voltage VDD.
Another problem arising in the conventional memory devices according to the art is that they require reference rows and constraints on the charge pump. Further, they require a power supply voltage of VDD/2 to pre-charge the reference store capacitor in the conventional sense amplifier. Uncontrolled variations in the reference signal may also arise. Some conventional memory devices according to the art implement a sense amplifier using a large number of dummy rows, which represent an overhead in the silicon area necessary to provide the memory circuit. A high complexity is often associated with the generation of reference rows and reference pre-charging signals and constraints exist on the charge pump to support the high voltage that drives the dummy rows. An extra power supply of VDD/2 is necessary to pre-charge the reference store capacitor of the dummy rows.
There is therefore a need for an improved memory circuit overcoming the above mentioned disadvantages of the memory circuits according to the art.